This application claims the priority of Korean Patent Application No. 2003-87991, filed on Dec. 5, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a system on a chip (SoC) and, more particularly to an apparatus and a method of managing a reconfiguration data memory when a reconfigurable SoC is constructed.
2. Description of the Related Art
Recently, a demand for a system on a chip (SoC), especially, a reconfigurable SoC, has increased. The reconfigurable SoC includes an internal processor that takes charge of processing and control and utilizes a memory in various ways so as to realize a target system. Since there is a limit in the inner space of the SoC for the memory, a large-capacity memory is arranged outside the SoC to construct the target system. Internal and external memories of the SoC are indispensable to the target system based on the SoC. As the internal and external memories of the SoC, DRAMs, SRAMs, flash memories, EEPROMs and so are used. Furthermore, these memories are used for embedded software that is indispensable to the SoC.
FIG. 1 is a block diagram of a conventional reconfigurable SoC. Referring to FIG. 1, the reconfigurable SoC includes a micro process unit (MPU)/digital signal processor (DSP) 10, a reconfiguration logic 20, an application specific integrated circuit (ASIC) 30, and a data memory 40, which are organically connected.
The MPU/DSP 10 takes charge of processing and control of the SoC and accesses corresponding instructions of an instruction memory 15 and data of the data memory 40 if required. The reconfiguration logic 20 includes a common circuit 21 with respect to a part that can be commonly used for reconfigurable functions and a reconfiguration data processor 22 that connects the MPU/DSP 10 to the ASIC 30. The reconfiguration data processor 22 receives configuration data required for reconfiguration from a configuration data memory 25 and processes it to achieve the reconfigurable SoC. The ASIC 30 selects a specific one of various ASICs having functions the SoC requires.
As described above, to construct the reconfigurable SoC needs a physical space for the configuration data memory 25 required for reconfiguration. In a prior art, separate memories used only for reconfiguration are arranged inside and outside the SoC in order to manage a reconfiguration data memory, and the configuration data is stored in the separate memories. Especially, when the SoC employs a lot of internal processors in array form, lots of configuration data memories are needed. This increases the space occupied by the memories.